Scan chain design for shift power reduction in scan-based testing
نویسندگان
چکیده
منابع مشابه
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint
The full-scan design is considered to be the best DfT discipline [1]. It can be automated using commercially available design tools. Over the years, it has gained widespread acceptability in system design environments and is now commonly used to test digital circuitry in integrated circuits or System-on-Chip cores. However, scan-based architectures are expensive in power consumption as each tes...
متن کاملModeling Scan Chain Modifications For Scan-in Test Power Minimization
Rapid and reliable test of SOCs necessitates upfront consideration of the test power issues. Special attention should be paid to scanbased cores as the test power problem is more severe due to excessive switching activity stemming from scan chain transitions during shift operations. We propose a scan chain modification methodology that transforms the stimuli to be inserted to the scan chain thr...
متن کاملA Novel Scan Segmentation Design Method for Avoiding Shift Timing Failures in Scan Testing
High power consumption in scan testing can cause undue yield loss which has increasingly become a serious problem for deep-submicron VLSI circuits. Growing evidence attributes this problem to shift timing failures, which are primarily caused by excessive switching activity in the proximities of clock paths that tends to introduce severe clock skew due to IR-drop-induced delay increase. This pap...
متن کاملMultiple Scan Chain Design Technique for Power Reduction during Test Application in BIST
Multiple scan chain has been used in DFT (design for test) architectures primarily to reduce test application time. Since power is an emerging problem, in this paper, we present a design technique for multiple scan chain in BIST (Built-In Self Test) to reduce average power dissipation and test application time, while maintaining the fault coverage. First, we partition the scan chain into a set ...
متن کاملTest Power Reduction through Minimization of Scan Chain Transitions
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help red...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Science China Information Sciences
سال: 2011
ISSN: 1674-733X,1869-1919
DOI: 10.1007/s11432-011-4205-z